1. Field of the Invention
The present invention relates generally to an LSI package and an inner lead wiring method for same, and more particularly to a face up ball grid array (BGA) package and an inner lead wiring method for same.
2. Description of the Related Art
In recent years, as demand for smaller, cheaper LSI packages for use in electronic equipment has increased, the BGA package has come to replace the quad flat package (QFP) as the LSI package of choice due to its smaller surface area and greater ease of installation.
The face up BGA package in particular comprises a chip having a plurality of bonding pads and a package substrate for mounting the chip. A plurality of terminals are arranged on a grid on a surface of the package substrate on which the chip is mounted, and a plurality of lead pads are aligned around the periphery of the package substrate.
The plurality of bonding pads on the chip are connected by bonding wire to the corresponding respective lead pads on the package substrate and the plurality of lead pads are connected by inner leads to the corresponding respective terminals.
It should be noted that there is a limit to the length of the bonding wire. If the bonding wire is too long, then the resistance and inductance of the bonding wire increase to the point that the characteristics of the chip may be lost. In addition, assembly and production output may decline.
Accordingly, as the size of the chip mounted on the package substrate decreases the limitation on the length of the bonding wire results in the lead pads aligned around the periphery of the package substrate being positioned closer to the center of the package substrate.
However, as described above, with the face up BGA package the position of the lead pad changes according to the size of the chip mounted on the package substrate. As a result, it is very difficult to configure the package so that the same lead pad and terminal are securely connected without crossed wiring regardless of changes in the size of the chip, that is, so that so-called pin compatibility is maintained. Therefore a low-cost face up BGA package that maintains pin compatibility regardless of changes in the size of the chip is desirable.
With the conventional face up BGA package, attempts have been made to maintain pin compatibility by, for example, changing the position of the bonding pads provided on the chip or by using multilayer wiring of the inner leads connecting the lead pads and the terminals.
However, changing the position of the bonding pads according to the size of the chip requires altering the layout of the chip itself, which is time-consuming and costly.
Moreover, there is the additional problem that other types of package variations, for example pin grid array (PGA) QFP, are rendered unusable with the chip even when available, because the chip layout has been altered by the changing of the position of the bonding pads.
Additionally, multilayering of the inner lead wiring raises the cost of the package, offsetting the lower-cost advantage of the reduction in chip size that was one of the original reasons for adopting the BGA package in the first place.